(1) Field of the Invention
The present invention relates to an HBT (heterojunction bipolar transistor) and HFET (heterojunction field-effect transistor) integrated circuit (Bi-HFET) used as a high-frequency semiconductor device and to a manufacturing method thereof.
(2) Description of the Related Art
Heterojunction bipolar transistors (HBT) having semiconductors with large bandgaps in emitters have been brought into practical use as high-frequency analogue elements used in cellular phones and the like. Having low temperature dependence, InGaP/GaAs HBTS utilizing InGaP as emitters in particular are expected to enjoy more and more various applications to highly reliable devices.
Recently, research and development projects have advanced for integrated circuits integrating an HBT and a heterojunction field-effect transistor (HFET), so that a switch element (SW) including the HFET can control a power amplifier (PA) including the HBT. Thus, a Bi-HFET process technology which forms an HBT and an HFET on the same substrate has attracted attention. A typical Bi-HFET structure includes an HBT disposed on the topside (on a surface side) and an HFET disposed on the bottom side (on a rear-face side) with respect to a substrate. Such a structure, sharing the same n-GaAs layer with a sub-collector layer of the HBT and a cap layer of the HFET, can reduce the number of masks and lower steps in the structure.
In the sharing with the sub-collector layer and the cap layer, the sub-collector layer of the HBT has a characteristic advantage in that on-resistance of the HBT decreases as the sub-collector layer thickens; meanwhile, the cap layer of the HFET has a characteristic advantage in that the recess structure thereof can be refined as the cap layer thins, and thus on-resistance of the HFET can be decreased. Hence, the characteristic advantages between the HBT and the HFET mean a trade-off relationship. A semiconductor device described in Patent Reference 1 has been proposed as a technique to solve the above problem.
FIG. 4 is a cross-sectional view illustrating a structure of the semiconductor device described in Patent Reference 1. This semiconductor device has regions with an HBT and an HFET formed (respectively referred to as an HBT region and an HFET region). The HFET region and the HFET region are electrically separated by an injected element separating region 720.
In the HFET region, a GaAs/AlGaAs superlattice layer 402, an AlGaAs barrier layer 403, an InGaAs channel layer 404, an electron donor layer 406 and a GaAs cap layer 405 are sequentially stacked on a semi-insulating GaAs substrate 401. A source electrode 304 and a drain electrode 305 are formed on the GaAs cap layer 405, and a gate electrode 306 is formed on the electron donor layer 406.
In the HBT region, the GaAs/AlGaAs superlattice layer 402, the AlGaAs barrier layer 403, the InGaAs channel layer 404, the electron donor 406, a GaAs sub-collector layer 407 sharing the same layer with the GaAs cap layer 405, a GaAs collector layer 408, a GaAs base layer 409, an InGaP emitter layer 410, a GaAs emitter cap layer 411, and an InGaAs emitter contact layer 412 are sequentially stacked on the GaAs substrate 401. On the GaAs sub-collector layer 407, the GaAs base layer 409, and the InGaAs emitter contact layer 412, a collector electrode 203, a base electrode 202 and an emitter electrode 201 are formed, respectively.
In order to minimize characteristic degradation of the HBT and the HFET in accordance with the trade-off between the characteristic advantages of the HBT and the HFET, this semiconductor device defines that the GaAs sub-collector layer 407 sharing the same layer with the GaAs cap layer 405 is 300 nm in thickness. It is noted that the Patent Reference 1 (US 2005/0184310) provides a detailed description on a manufacturing method of the semiconductor device.